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[VHDL-FPGA-Verilograke_mrc

Description: 实现RAKE接收机的最大比合并准则,输入位宽16比特。-RAKE receiver to achieve the maximal ratio combining criteria, enter the 16-bit wide.
Platform: | Size: 2048 | Author: 黄虎 | Hits:

[VHDL-FPGA-VerilogViterbi_RAKE

Description: 这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
Platform: | Size: 8838144 | Author: 骆军 | Hits:

[Communication-MobileRAKE_Receiver

Description: rake receiver thesis
Platform: | Size: 665600 | Author: vlsi | Hits:

[Software EngineeringRAKE_FPGA

Description: RAKE技术与CDMA系统相结合,能够带来系统容量和通信质量的极大提 高。根据军事通信中对设备便携性及低功耗的特殊要求,本文研究了一种便携式 基站的收发系统,重点研究了其中的RAKE接收部分。给出了系统的发送方案和 接收方案,对接收机部分所涉及的关键技术和算法,包括数字下变频技术、匹配相关技术、多径搜索技术、信道估计技术、解调及多径合并技术进行了较为详细的分析和说明。在此基础上,运用VHDL语言进行了硬件平台上FPGA部分的功能实现,并对整个系统进行了调试,给出了一些相关的仿真及测试结果。最后对该系统还需进一步研究的问题进行了简要的介绍,对调试过程中的出现的一些问题进行了简单的分析和小结。 -CDMA system with RAKE combining technology, can bring the system capacity and communication quality significantly raised High. According to military communications equipment portability and low power consumption special requirements, this paper, a portable The base station transceiver system, which focuses on the RAKE receiving part. Then the system sends the program and Receiving scheme, the receiver part of the key technologies involved and algorithms, including digital down-conversion technology, matching the relevant technology, multi-path search and channel estimation, demodulation and multi-path merging techniques on a more detailed analysis and explanation. On this basis, the use of VHDL, FPGA hardware platform to achieve some functionality, and debugging the system, given some of the relevant simulation and test results. Finally the system need further study are briefly introduced, and the emergence of the process of debugging some problems in a simple analysis and summar
Platform: | Size: 2499584 | Author: 徐进 | Hits:

[VHDL-FPGA-VerilogRake_Receiver

Description: 用Verilog HDL语言实现一个Rake接收机的最大比合并准则,其中3路输入数据是并行相关输出-Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output
Platform: | Size: 1024 | Author: 张茂磊 | Hits:

[VHDL-FPGA-VerilogRake-receive

Description: 本文介绍的一种基于多载波扩频通信的Rake接收机工作原理以及设计思想,并用FPGA技术加以实现-This article describes a multi-carrier spread spectrum based communication works as well as Rake receiver design and implementation with FPGA technology to
Platform: | Size: 232448 | Author: 杨帆 | Hits:

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